Three-dimensional structure NAND flash memories manufactured with BiCS technique manufacturing processes are known. Such memories use a structure to allow multiple memory strings to share word lines to reduce the number of transistors for selecting a specific word line, and therefore reduce the area thereof. In contrast, interconnects for select gates are provided for each memory string. The purpose is to allow for selecting one memory string among the memory strings since memory strings which share word lines are also coupled to the same bit line. In this way, various disturbs resulting from the word-line sharing are prevented to realize desired operations.